Turbo coding is frequently applied to modern communication systems because of low power and narrow bandwidth requirement. One characteristic of turbo coding is that there is an interleaver used to re-arrange the order of a plurality of data in a data frame prior to data transmission.
Under the regulation of 3GPP, data are processed, or interleaved, by referring to four parameters: a row parameter, a column parameter, a prime parameter and a primitive parameter. The row and column parameters are configured to generate a new column address. The column, prime and primitive parameters are configured to generate a new row address. According to the new column and row addresses, the interleaver interleaves the data.
FIG. 1 shows a block diagram of an interleaver implemented for 3GPP. The interleaver includes an interleaver parameter calculator 101, a column address generator 103, a row address generator 105 and an adder 107. The interleaver parameter calculator 101 is configured to receive a datum 100, and, according to the datum 100, to calculate to output a row parameter 102, a column parameter 104, a prime parameter 106 and a primitive parameter 108. The column address generator 103 is configured to receive the row parameter 102 and the column parameter 104 to generate a column address 110. The row address generator 105 is configured to receive the column parameter 104, the prime parameter 106 and the primitive parameter 108 to generate a row address 112. The column address 110 and the row address 112, after being calculated by the adder 107, form an interleaving address 114, which is used to interleave the datum 100.
The interleaver parameter calculator 101 of the prior art includes a table configured to store all available values of the four parameters 102, 104, 106 and 108. Under the regulation of 3GPP, the row parameter 102, the column parameter 104, the prime parameter 106 and the primitive parameter 108 are respectively 5 bits, 9 bits, 9 bits and 5 bits, and the valid sizes of a data frame are in a range from 40 to 5114, which means that the table has 5075 rows. Therefore, the table of the interleaver parameter calculator 101 needs a total of (5+9+9+5)×5075=142100 bits. When the interleaver is implemented by means of VLSI technology, cost will stay high because the table occupies a large IC area.